Spacequanta

A layered 7-bit decoder reaches 1% frame errors at 2.25 dB in 10 iterations. A flooding decoder needs more than 3 dB.

Measured in simulation on the CCSDS AR4JA code (rate 1/2, 1024 information bits, 2048 transmitted). Explore the curves below.

Simulation and model-based estimates only. Nothing here has been synthesized or run on hardware, so this is TRL 2 to early 3.

Channel

Iteration cap

Scheduling matters most. At 10 iterations a layered float decoder needs 2.21 dB for 1% frame errors. A flooding decoder does not get there by 3 dB.
7 bits is enough. A 7-bit layered decoder is within about 0.04 dB of floating point. 6 bits costs about 0.1 dB, and 5 bits costs 0.35 to 0.5 dB.
Bursts cost about 0.45 dB. The burst model drops contiguous runs of symbols (mean length 16, 3% of symbols in total).

Eb/N0 needed for 1% frame errors

Values are in dB, interpolated between simulated points, so treat them as plus or minus 0.1 dB. A dash means the decoder did not reach 1% within the simulated range.

What this could cost in hardware

A pipelined, layered decoder processing 64 or 128 checks in parallel. The cycle model is driven by the real parity-check matrix and reproduces the 240 clocks per iteration of a published commercial decoder.

Model-based estimate, not a synthesis result. The clock frequencies are borrowed from published designs. Flight-grade FPGAs typically run slower.

Parallel checks

Pipeline depth (cycles)

Operating point

Worst-case iteration cap: 20

Clock: 92 MHz

clocks per iteration

clocks per frame, average

information throughput, average

latency, average

latency at the iteration cap

estimated logic (plus or minus 25%)

How these numbers were checked

The AR4JA code was built from the standard's tables, with dimensions, rank, degree profile and girth checked.
A 60,000-frame run at 2.2 dB showed no frame errors at 50 iterations (9 at 20 iterations, 717 at 10). That is consistent with a vendor-quoted 1e-5 at about 2.2 dB, though this run cannot resolve 1e-5.
The cycle model matches a published decoder's 240 clocks per iteration exactly. Realistic hardware schedules decode as well as an idealized one, at about 8.3 average iterations at 2.0 dB.

Limits

The decoder is my own implementation, written for this benchmark, and the burst channel is a model I chose, not measured link data.
Results are for one code. Payloads may use other standards, so the numbers must be rerun on the code actually used.
Hardware figures are estimates. Radiation mitigation such as triple redundancy would add area.